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ygv628b avdp7 advanced video display processor 7 ygv628b catalo g catalog no.: ls i -4gv628b20 2005.7 o o u u t t l l i i n n e e ygv628b (hereafter called avdp7) is the latest version of yamaha avdp series which has many past successful records in various visual equipments, vehicle equipment , etc. three bit-map planes are equipped, and it can be displayed in piles to an external image; furthermore, avdp7 has many functions as osd (on screen display), such as -blending, change of a display priority, etc. in addition, it has a digital image input/output function to allow an external image to be expanded or reduced. moreover, avdp7 is supports to the resolution up to svga, and it is possible to apply to the various digital equipments only by connecting one sdram to an external memory as a frame memory. f f e e a a t t u u r r e e osd function the osd images which is composed of plains in case of a digital image input is overlaid. simultaneous use of three plains is possible in avdp7 at its maximum. the natural picture display of 65536 colors by r5bit, g6bit, and b5bit. it is the palette color of 256 colors in 16777216 colors. supports 16bit ycrcb422 16 gray-levels of -blending in dot units conversion of display priority is possible display resolution creation of the display timing of ntsc, pal, qvga, wide qvga, vga, wide vga, and svga is possible. examples of correspondence resolution : 320240, 400240, 720240, 640480, 800480, 800600, etc.. resolution converting function : horizontal direction ? 1/2 times to 8192 times display vertical direction ? 1/4 times to 8192 times display.
ygv628b -2- digital image input/output function corresponding to 18bit rgb, 16bit ycrcb422, and itu656. by ys bit output, mixing with an image signal are possible externally. analog image output function analog rgb output which has 8 bits dac for each r,g,b by ys bit output, super-impose of image data is available from an outside. capture function the depiction from the external image input of 18bit rgb, 16bit ycrcb422, and itu656 to frame memory is possible in real time. when the digital image input is itu656, it is possible to select from two systems of asynchronous input. pixel skipping functions of horizontal direction an d vertical direction. interlace ? progressive conversion function external memory video memory 16mbit, 64mbit, 128mbit, and 256mbit(x16) of sdram are connectable. however, only a half domain is possible to use at the time of 256mbits of sdram is in use. write/read access by the memory transfer function the maximum operating frequency of sdram clock is 81mhz. others high flexibility cpu i/f with 16bit cpu bus width and endian control are adopted. built-in register is directly mapped to the 256 bytes of cpu memory space. 176 pin plastic lqfp pin lead coating is pb free. (YGV628B-VZ) operating temperature: -40 degree to +85 degree. cmos, 3.3v unity voltage(5v tolerant)
ygv628b -3- b b l l o o c c k k d d i i a a g g r r a a m m monitor i/f r, g, b dbo5 iref csync_n vsync _n blank_n gck1out gck2out registers to all blocks clock syckin video memory i/f video input i/f dri[5:0] dgi[5:0] dbi[5:0] hsin_n vsin_n gck1in gck2in dac monitor i/f r, g, b dro5-0 dgo5-0 dbo5-0 iref csync_n vsync_n blank_n gck1out gck2out crtc dma control color palette registers to all blocks cpu interface clock syckin video memory i/f priority enc. video input i/f dri[5:0] dgi[5:0] dbi[5:0] hsin_n vsin_n gck1in gck2in video memory interface bitmap fifo data format conv. filter video capture controller video input interface data format conv. to clock gen. to crtc alpha blending data format conv. dac dac clock gen. cpu i/f wrh_n wrl_n rd_n wait_n int_n dreq_n cpu i/f d[15:0] a[23:1] cs_n ready_n reset_n sa[13:0] scs_n ras_n cas_n we_n udqm ldqm sdckout sdq[15:0] e e x x a a m m p p l l e e s s o o f f s s y y s s t t e e m m c c o o m m p p o o s s i i t t i i o o n n z independent ( self-propelled) system avdp7 rom ram cpu dot clock sdram crt lcd encoder analog rgb digital rgb z example of osd to digital image (cpu, sdram, etc. are omitted) avdp7 dac ntsc encoder image + osd external image [16bitycrcb] [itu656] [16bitycrcb] [itu656] separate composite component
ygv628b -4- z example of osd to analog image (cpu, sdram, etc. are omitted) avdp7 analog switch [analog rgb] analog image analog image 13.5mhz hsync,vsync ys_n z example of application to liquid crystal television (cpu, sdram, etc. are omitted) avdp7 image + osd external image [16bitycrcb] [18bitrgb] lcd e.g.) 640x480 ntsc decoder external image [ntsc] capture + interlace progressive conversion z example of application to on-board multi-vision (cpu, sdram, etc. are omitted) avdp7 image + osd tv external image [18bitrgb] [18bitrgb] lcd e.g.) 800x480 capture + resolution conversion e.g.) ~ 720x480/2 [4:3] ~ 720x360/2 [16:9] ~ 720x346/2 [1.85:1] ~ 720x270/2 [2.35:1] [ ]= aspect ratio 800x480 [16bitycrcb] [itu656]
ygv628b -5- z example of application to digital image equipment (cpu, sdram, etc. are omitted) image+osd [itu656] [itu656] analog image avdp7 image through [itu656] [itu656] digital image ntsc decoder mpeg decoder crt / lcd aux. video z example of application to digital recording equipment (cpu, sdram, etc. are omitted) image + osd [itu656] [itu656] crt / lcd broadcasting image image through [itu656] [itu656] recorded image avdp7 mpeg decoder recording system mpeg encoder
ygv628b -6- p p i i n n t t a a b b l l e e pins name numbers i/o functions level 5tr drive cup interface d15-0 16 i/o cpu data bus lvttl 4ma a23-1 23 i cpu address bus lvttl cs_n 1 i chip select lvttl rd_n 1 i read pulse input lvttl wrh_n 1 i write strobe input/d15-8 lvttl wrl_n 1 i write strobe input/d7-0 lvttl wait_n 1 o cpu bus wait (3-state output) lvttl 4ma ready_n 1 o cpu bus ready (3-state output) lvttl 4ma int_n 1 o interrupt lvttl 4ma dreq_n 1 o direct memory access lvttl 4ma reset_n 1 i reset input lvcmos video memory interface sdq15-0 16 i/o video memory data bus lvttl 4ma sa13-0 14 o video memory address bus lvttl 4ma scs_n 1 o video memory chip enable lvttl 4ma ras_n 1 o video memory low address strobe output lvttl 4ma cas_n 1 o video memory column address strobe output lvttl 4ma we_n 1 o video memory write enable lvttl 4ma udqm 1 o video memory data mask output/ sdq15-8 lvttl 4ma ldqm 1 o video memory data mask output/ sdq7-0 lvttl 4ma sdckout 1 o video memory clock output lvttl 8ma monitor interface r,g,b 3 o analog r, g, b, signals output analog iref 1 - dac reference electric-current input analog dri5-0 6 i digital r signal input lvttl dgi5-0 6 i digital g signal input lvttl dbi5-0 6 i digital b signal input lvttl hsin_n 1 i horizontal synchronized signal input lvttl vsin_n 1 i vertical synchronized signal input lvttl ys_n 1 o ys signal output lvttl 4ma dro5-0 6 o digital r signal output lvttl 4ma dgo5-0 6 o digital g signal output lvttl 4ma dbo5-0 6 o digital b signal output lvttl 4ma vsync_n 1 o vertical synchronized signal output lvttl 4ma csync_n 1 o horizontal synchronized signal / compound synchronized signal output lvttl 4ma blank_n 1 o non-display interval output lvttl 4ma gck1out 1 o dot clock output 1 lvttl 4ma gck2out 1 o dot clock output 2 lvttl 4ma 5tr : 5v supply yes/no yes ? / no ? drive driving capability
ygv628b -7- pins name numbers i/o functions level 5tr drive clock gck1in 1 i dot clock input1 lvttl gck2in 1 i dot clock input 2 lvttl synckin 1 i system clock input lvttl filter 1 - filter connect pin for pll analog power supply vdd 15 - power supply for digital circuit part vss 17 - ground for digital circuit part pllvdd 1 - analog power supply for built-in pll pllvss 1 - ground for built-in pll dacvdd 1 - analog power supply for built-in dac dacvss 1 - analog ground for built-in dac test pin test2-0_n 3 i test pin: input h level lvttl 5tr : 5v supply yes/no yes ? / no ? drive driving capability
ygv628b -8- p p i i n n a a s s s s i i g g n n m m e e n n t t a23 a9 vdd a8 a7 a6 a5 a4 a3 a2 a1 rd_n wrl_n cs_n reset_n ready_n int_n sdq0 a22 a21 a20 a19 vss a18 a17 a16 a15 a14 a13 a12 a11 a10 vdd vss wrh_n vss vdd dreq_n wait_n d15 d14 d13 d12 d11 vss vdd d9 d8 d7 d6 d5 d2 d1 d0 d4 d3 d10 vss vdd sdq15 vss sdq1 sdq14 sdq2 sdq13 sdq3 vss sdq12 sdq11 sdq10 vdd sdq8 sdq9 sdq6 sdq7 sdq4 sdq5 vss vdd ldqm vss we_n udqm cas_n sdckout ras_n vss scs_n blank_n vdd dacvss r g b iref dacvdd test2_n test0_n test1_n csync_n vsync_n gck1out vdd gck2in dri0 dri1 dri2 dri3 dri4 dri5 vss dgi1 dgi2 dgi3 dgi4 dgi5 dgi0 vdd vss dbi1 dbi2 dbi3 dbi4 dbi5 dbi0 hsin_n vsin_n vdd vss gck1in syckin pllvdd pllvss filter ys_n dbo5 dbo4 vss dbo3 dbo2 dbo1 dbo0 dbo5 dbo4 vdd dgo3 dgo2 vss dgo1 dgo0 dro5 dro4 dro3 dro2 dro1 dro0 vdd gck2out vss sa4 sa3 sa5 sa2 vdd sa7 sa6 sa1 vss sa0 sa8 sa10 sa9 sa12 sa11 vdd sa13 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 109 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 82 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 38 39 40 41 42 43 44 30 31 32 33 34 35 36 37 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
ygv628b -9- p p i i n n a a s s s s i i g g n n m m e e n n t t t t a a b b l l e e no. terminal name i/o no. terminal name i/o no. terminal name i/o no. terminal name i/o 1 a23 i 45 d10 i/o 89 sa13 o 133 dacvss 2 a22 i 46 vdd 90 vdd 134 r o 3 a21 i 47 d9 i/o 91 sa11 o 135 g o 4 a20 i 48 d8 i/o 92 sa12 o 136 b o 5 vdd 49 d7 i/o 93 sa9 o 137 iref 6 a19 i 50 d6 i/o 94 sa10 o 138 dacvdd 7 vss 51 d5 i/o 95 sa8 o 139 test2_n i 8 a18 i 52 d4 i/o 96 sa0 o 140 test1_n i 9 a17 i 53 vss 97 vss 141 test0_n i 10 a16 i 54 d3 i/o 98 sa1 o 142 csync_n o 11 a15 i 55 d2 i/o 99 sa6 o 143 vsync_n o 12 a14 i 56 d1 i/o 100 sa7 o 144 gck1out o 13 a13 i 57 d0 i/o 101 vdd 145 vdd 14 a12 i 58 vdd 102 sa2 o 146 gck2in i 15 a11 i 59 sdq0 i/o 103 sa5 o 147 dri0 i 16 a10 i 60 sdq15 i/o 104 sa3 o 148 vss 17 a9 i 61 vss 105 sa4 o 149 dri1 i 18 a8 i 62 sdq1 i/o 106 vss 150 dri2 i 19 vdd 63 sdq14 i/o 107 gck2out o 151 dri3 i 20 vss 64 sdq2 i/o 108 vdd 152 dri4 i 21 a7 i 65 sdq13 i/o 109 dro0 o 153 dri5 i 22 a6 i 66 sdq3 i/o 110 dro1 o 154 dgi0 i 23 a5 i 67 vss 111 dro2 o 155 dgi1 i 24 a4 i 68 sdq12 i/o 112 dro3 o 156 dgi2 i 25 a3 i 69 vdd 113 dro4 o 157 dgi3 i 26 a2 i 70 sdq4 i/o 114 dro5 o 158 vdd 27 a1 i 71 sdq11 i/o 115 dgo0 o 159 dgi4 i 28 wrh_n i 72 sdq5 i/o 116 dgo1 o 160 vss 29 wrl_n i 73 sdq10 i/o 117 vss 161 dgi5 i 30 rd_n i 74 vss 118 dgo2 o 162 dbi0 i 31 reset_n ist 75 sdq6 i/o 119 dgo3 o 163 dbi1 i 32 vss 76 sdq9 i/o 120 vdd 164 dbi2 i 33 cs_n i 77 sdq7 i/o 121 dgo4 o 165 dbi3 i 34 vdd 78 sdq8 i/o 122 dgo5 o 166 dbi4 i 35 dreq_n o 79 vdd 123 dbo0 o 167 dbi5 i 36 int_n o 80 ldqm o 124 dbo1 o 168 hsin_n i 37 ready_n ot 81 vss 125 dbo2 o 169 vsin_n i 38 wait_n ot 82 we_n o 126 dbo3 o 170 vdd 39 d15 i/o 83 udqm o 127 vss 171 vss 40 d14 i/o 84 cas_n o 128 dbo4 o 172 gck1in i 41 d13 i/o 85 sdckout o 129 dbo5 o 173 syckin i 42 d12 i/o 86 ras_n o 130 ys_n o 174 pllvdd 43 vss 87 vss 131 blank_n o 175 pllvss 44 d11 i/o 88 scs_n o 132 vdd 176 filter i : input, 1 st : schmitt trigger input, o : output, od : open drain output, ot : 3-state output, i/o : input/output
ygv628b -10- p p i i n n s s f f u u n n c c t t i i o o n n s s avdp7 operates with a 3.3v power supply. therefore, input and output of the interface to the peripheral circuits operates at lvttl (3.3v)except reset_n pin. however, the tolerant voltage to input/output signals are guaranteed up to 5v, therefore, connection to a 5v tll level compatible device is also possible. please use a register separately for each pin when making pull-up or pull-down of i/o pins outside of the device. however, when an input signal is fixed by pull-up or pull-down resistor, a common resistor can be used for these input pins. 1 1 ) ) p p o o w w e e r r s s u u p p p p l l y y avdp7 is the 3.3v single power supply specification. in addition, exclusive analog power supply pins are prepared for the built-in pll and the built-in dac respectively. be sure to observe the following instructions when performing power-on and power-off. simultaneous power-on and power-off is the rule. when a time difference occurs due to the design, please follow the following order of power-on and power-off. please perform power-on and power-off so that pllvdd does not become higher than vdd. the order of power-on and power-off. at the time of power-on. vdd (digital power supply) ? pllvdd (analog power supply for pll) ? dacvdd (analog power supply for dac) ? signals . at the time of power-off signals ? dacvdd (analog power supply for dac) ? pllvdd (analog power supply for pll) ? vdd (digital power supply). when power-on and power-off are performed in reverse order against a recommended procedure in two kinds of power supplies in any of the power supplies mentioned above, a problem might be occurred to have an influence on the reliability of lsi. for the reason, please avoid such operations. vdd (power supply pin no.5, 19, 34,46, 58, 69, 79, 90, 101, 108, 120, 132, 145, 158, 170) vss (power supply pin no.7, 20, 32, 43, 53, 61, 67, 74, 81, 87, 97, 106, 117, 127, 148, 160, 171) power supply pin for internal digital circuit. please supply 3.3v to vdd pins, and supply a ground level to vss pin. pllvdd (power supply pin no.174) pllvss (power supply pin no.175) it is an analog power supply pin for built-in pll. please supply a ground level to pllvss pins, and supply 3.3v to pllvdd. be sure to perform power supply power-on and power-off, so that pllvdd may not become higher than vdd. dacvdd (power supply pin no.138) dacvss (power supply pin no.133) it is an analog power supply pin for built-in dac. please supply 3.3v to dacvdd pin, and supply a ground level to dacvss pin. be sure to supply separately to other power supplies.
ygv628b -11- 2 2 ) ) c c l l o o c c k k to avdp7, a clock (dot clock) for a scan timing of monitor display, and for passing a display data, a clock (capture clock) for capturing a digital image input, and a clock (sys tem clock) which is used for other process are supplied separately. please input a dot clock and a capture clock into gck1in pin and gck2in pin, and input a system clock into syckin pin. since there is no function of xtal oscillation, be sure to input the clock which carried out the external oscillation. gck1in (input pin no.172) gck2in (input pin no.146) - these are input pins of a dot clock and a capture clock. - be sure to input the 5mhz to 40mhz clock oscillated externally into these pins. syckin (input pin no. 173) - it is a system clock input pin. the reference clock for the built-in pll is input. - be sure to input the 5mhz to 40mhz clock into syckin. filter (analog pin no.176) - it is the filter connection pin for built-in pll used for a system clock oscillation. - please connect a resistor and a capacitor externally between pllvss pin and filter pin. 3 3 ) ) c c p p u u i i n n t t e e r r f f a a c c e e d15-0 (input/output pin no. 39-42, 44, 45, 47-52, 54-57) - it is a cpu data bus pin. it connects with an external data bus of cpu. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device. a23-1 (input pin no. 1-4, 6, 8-18, 21-27) - it is a cpu address bus pin. it connects with an external address bus of cpu. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. cs_n (input pin no.33) - it is a chip select input pin. - the chip select signals from cpu to register space or video memory space are input. - since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. - this signal is low active. rd_n (input pin no.30) - it is a read pulse input pin. - the strobe signal for data read-out from cpu is input. - since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. - this signal is low active. wrh_n (input pin no.28) wrl_n (input pin no. 29) - it is a write pulse input pin. the strobe signal for data writing from cpu is input. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary.
ygv628b -12- - these signals are low active. wait_n (3-state output pin no.38) - it is a cpu bus wait pin. - the bus wait demand signal to cpu is output. - since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device. - this signal is low active. ready_n (3-state output pin no.37) - it is a cpu bus ready pin. - the bus ready signal to cpu is output. - since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device. - this signal is low active. int_n (output pin no.36) - it is an interrupt signal output pin. - the interrupt request signal to cpu is output. - this signal is low active. dreq_n (output pin no.35) - it is a dma request signal output pin. - the dma request signal to cpu is output. - this signal is low active. 4) video memory interface sdq15-0 (input/output pin no. 59, 60, 62-66, 68, 70-73, 75-78) - it is a data input/output bus pin for video memories. - it connects with the data bus of a video memory. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device. sa13-0 (output pin no. 89, 91-96, 98-100, 102-105) - it is an address bus output pin for video memories. - it connects with the address bus of a video memory. - the signal attribute output from sa13-0 pin differs according to the kind of external sdram. scs_n (output pin no.88) - it is a tip select output pin for video memories. - the tip select signal to a video memory is output. - this signal is low active. ras_n (output pin no.86) - it is a low address strobe output pin for video memories. - the low address strobe signal to a video memory is output. - this signal is low active. cas_n (output pin no.84) - it is a column address strobe output pin for video memories. - the column address strobe signal to a video memory is output. - this signal is low active. we_n (output pin no.82) - it is a write strobe output pin for video memories. - the write strobe signal to a video memory is output. - this signal is low active.
ygv628b -13- udqm (output pin no.83) ldqm (output pin no.80) - it is a data mask signal output pin for video memories. - the data mask signal to a video memory is output. - udqm pin is a data mask signal sdq15-8 pin, and ldqm pin is a data make signal to sdq7-0. - these signals are high active. sdckout (output pin no.85) - it is a clock output pin for video memories. - the clock to a video memory is output. - the clock frequency output from this pin is 75mhz to 81mhz. 5 5 ) ) m m o o n n i i t t o o r r i i n n t t e e r r f f a a c c e e r (analog output pin no.134) g (analog output pin no.135) b (analog output pin no.136) - it is an analog rgb output pin. - linear r, g, and b signal are output. - when the analog rgb output is not used, please connect nothing. iref (analog pin no.137) - it is a standard current input pin for rgb dac. - when an analog rgb output is not used, please connect nothing. dro5-0 (output pin no.109-114) dgo5-0 (output pin no.115, 116, 118, 119, 121, 122) dbo5-0 (output pin no.123-126, 128, 129) - it is a digital rgb output pin. - when a digital rgb output is not used, please connect nothing. dri5-0 (input pin no.147, 149-153) dgi5-0 (input pin no.154-157, 159, 161) dbi5-0 (input pin no.162-167) - it is a digital rgb input pin. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. vsync_n (output pin no.143) - it is a vertical synchronized signal output pin. - vertical synchronized signal is output. - this signal is low active. csync_n (output pin no.142) - it is a horizontal / composite synchronized signal output pin. - horizontal synchronized signal or composite synchronized signal are output. - this signal is low active. hsin_n (input pin no.168) - it is a horizontal synchronized signal input pin. - the external horizontal synchronized signal for rese tting an internal horizontal counter is input. - when not used, please make the pull-up outside of the device if necessary because this pin does not internally have a pull-up resistor.
ygv628b -14- - this signal is low active. vsin_n (input pin no.169) - it is a vertical synchronized signal input pin. - the external vertical synchronized signal for resetting an internal vertical counter is input. - when not used, please make the pull-up outside of the device if necessary because this pin does not internally have a pull-up resistor. - this signal is low active. blank_n (output pin no.131) - it is a display timing output pin. - the signal which shows a no-display period is output. - this signal is low active. ys_n (output pin no.130) - it is ys signal output pin. - ys signal at the time of superimpose is output. - this signal is low active. gck1out (output pin no.144) gck2out (output pin no.107) - it is a dot clock output pin. - a dot clock is output. 6 6 ) ) s s y y s s t t e e m m r r e e s s e e t t reset_n (schmitt trigger type input pin no.31) - it is a reset pin. - please input a power-on reset signal. - the reset signal input having predetermined period is surely required at the power-on. - since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. - this signal is low active. this pin uses the schmitt trigger type buffer. 7 7 ) ) l l s s i i t t e e s s t t test2-0_n (input pin no. 139, 140, 141) - it is a test mode setting pin for a device test. - since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device.
ygv628b -15- e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s absolute maximum ratings items symbol rating unit note power supply voltage (vdd pin) v dd -0.5 to +4.6 v 1 dac power supply voltage (dacvdd pin) v dac -0.5 to +4.6 v 1 pll power supply voltage(pllvdd pin) v pll -0.5 to +4.6 v 1 input pin voltage v i -0.5 to +5.5 v 1 output pin voltage (5v tolerant pin) v o -0.5 to +5.5 v 1 output pin voltage (other than above) v o -0.5 to v dd +0.5 v 1 output pin electric current i o -20 to +20 ma storage temperature t stg -50 to +125 c note 1) value based on vss(gnd) =0v recommended operating condition items symbol min typ max unit note power supply voltage v dd 3.0 3.3 3.6 v 1 dac power supply voltage (dacvdd pin) v dac 3.0 3.3 3.6 v 1 pll power supply voltage (pllvdd pin) v pll 3.0 3.3 3.6 v 1 ambient operation temperature t op -40 +85 c 2 note 1) value based on vss(gnd) =0v note 2) the board wiring density is estimated to be 260% or over.
ygv628b -16- dc characteristics items symbol min typ max unit note low level input voltage (reset_n pin, test2-0_n pin) v il -0.3 v dd 0.2 v 1 low level input voltage (except reset_n pin, test2-0_n pin) v il -0.3 0.8 v 1 high level input voltage (reset_n pin, test2-0_n pin) v ih v dd 0.8 5.5 v 1 high level input voltage (except reset_n pin, test2-0_n pin) v ih 2.0 5.5 v 1 built-in dac recommended operation condition reference current (iref pin) -9.38 ma output load (r,g,b) 37.5 ? note 1) value based on vss(gnd) =0v items condition symbol min typ max unit note low level output voltage i ol =100a v ol 0 0.4 v high level output voltage i oh = -100a v oh 2.4 v dd v input leakage current i li -10 +10 a 2 output leakage current i lo -25 +25 a total power consumption c l =20pf p d 1.2 w 3 consumption current items vdd c l =20pf i vdd 230 ma 3 dacvdd when 0v output i dac 80 ma 3 pllvdd when 81mhz i pll 2.5 ma 3 note 2) be sure to use the resistance less than 7k ? when connecting an external pull-up resistance. the minimum and the maximum of input leak current are a value when having not connected external resistance. note 3) v il = gnd, v ih = v dd for consumption current and power consumption value. items symbol min typ max unit input pin capacitance c i 10 pf output pin capacitance c o 10 pf input/output pin capacitance c io 10 pf
ygv628b -17- ac characteristics note : a timing measurement level is 1.4v and input signal transient time is 1ns. clock input no. item symbol min typ max unit syckin input clock frequency f syck 5 40 mhz 1 syckin clock cycle time t csyck 25 200 ns 2 syckin clock high level pulse width t whsyck 7.5 ns 3 syckin clock low level pulse width t wlsyck 7.5 ns mclk(pll out) clock frequency f mclk 75 81 mhz 4 mclk(pll out) clock cycle time t cmclk 13.3 12.3 ns 1.4v 1 23 reset input and power supply no. item symbol min typ max unit 1 reset_n pin input time (respect to syckin) t wres1 1 s 2 reset_n pin input time (respect to vdd) t wres2 1 s 3 vdd-reset_n pin setup time t sres 0 s 4 pll lock up time t wplu 10 ms 5 time difference in power-on t vskwr 1 s 6 time difference in power-off t vskwf 1 s power supply rose up last reset_n r_sr1 syckin 1 pll playback clock 4 5 50% of the recommended operating voltage (typ) vil 50% of the recommended operating voltage (typ) 3 vil vih min. of the recommended operating voltage 2 power supply rose up first power supply fell down last 6 50% of the recommended operating voltage (typ) 50% of the recommended operating voltage (typ) power supply fell down first
ygv628b -18- cpu interface (measurement condition : cl=20pf) no. item symbol min typ max unit note 1 a23-1 : setup time t sa 1 1 2 a23-1 : hold time t ha 0 1 3 cs_n: setup time t scs 1 2 4 cs_n: hold time t hcs 0 2 5 d15-0 : output data turn on time t ond 0 6 d15-0 : output data turn off time t offd 10 7 d15-0 : output data valid delay time t dd 0 8 d15-0 : output data hold time t hd 0 9 wait_n, ready_n: turn on time t onwait 0 10 wait_n, ready_n: valid delay time t dwait 15 11 wait_n,ready_n: turn off time t offwait 15 12 d15-0 : input data setup time t sd t cmclk +10 3 13 d15-0 : input data hold time t hd 0 3 14 wrx_n: hold time t hwr 0 15 ready_n: hold time from wrx_n, rd_n inactive t hready 0 12 ns note 1) this is a regulation for wrh_n, wrl_n, and rd_n signals. however, in case of cs_n control, it is a rule for cs_n. note 2) they are the conditions of being wrh_n, wrl_n, and rd_n control. it becomes cs_n control when not filling this regulation. note 3) d15-8 is the regulation to wrh_n. d7-0 is the regulation to wrl_n. cpu read cycle a23-1 cs_n rd_n d15-0 wait _n ready_n 1 4 2 5 3 6 9 711 10 8 hi gh-z high-z hi gh-z high-z 9 711 hi gh-z high-z 15
ygv628b -19- cpu write cycle a23-1 cs_n wrx_n d15-0 wait_n ready_n 1 4 2 12 3 13 14 11 9 10 high-z high-z 9 11 10 hi gh-z hi gh-z 15
ygv628b -20- sdram interface (measurement condition: cl=15pf) no. item symbol min typ max unit note 1 sdckout: jitter t jsdck -1 1 ns 1 sdckout: frequency f sdck 75 81 mhz 1,2 2 sdckout: cycle time t csdck 12.35 13.33 1,3 3 sdckout: clock high level width t whsdck 3.5 1 4 sdckout: clock low level width t wlsdck 3.5 1 5 sdq15-0 : input data setup time t ssdq 4 1 6 sdq15-0 : input data hold time t hsdq 1 1 7 scs_n, ras_n, cas_n, we_n, sa13-0, sdq15-0, udqm, ldqm : output delay time t dsdo 9 1 8 scs_n, ras_n, cas_n, we_n, sa13-0, sdq15-0, udqm, ldqm : output hold time t hsdo 1.5 ns 1 contents of mode register read/write mode burst read and burst write cas latency 2 wrap type sequential burst length 2 command interval 4 clock cycle time (c l =2) t ck2 less than 10 ns ref/active ? ref/active command interval t rc six or less cycle (in case of sdckout frequency 81 mhz, less than 74ns) 5 pre-charge ? active command interval t rp two or less cycle (in case of sdckout frequency 81 mhz, less than 24ns) write recovery time t wr two or less cycle (in case of sdckout frequency 81 mhz, less than 24ns) data in ? command interval t dal four or less cycle (in case of sdckout frequency 81 mhz, less than 49ns) active ? pre-charge command interval t ras five or less cycle (in case of sdckout frequency 81 mhz, less than 61ns) active ? read / write command delay time t rcd two or less cycle (in case of sdckout frequency 81 mhz, less than 24ns) mode register set cycle time t rsc four or less cycle (in case of sdckout frequency 81 mhz, less than 49ns) note 1) pll must be in stable state. note 2) fulfill a condition ? f sdck ? f gck1o 2 note 3) fulfill a condition ? t csdck 2 ? t cgck1o note 4) conditions of sdram to be chosen. note 5) although some sdram makers may have divided and specified the interval from the auto-refresh to the following command (t rrc ), it is necessary to be lower than t rc .
ygv628b -21- sdckout sdq[15:0] (input) outputs 7 8 3 4 2 5 6 1 1 outputs scs_n, ras_n, cas_n, we_n, sa13-0, sdq15-0(output), udqm, ldqm
ygv628b -22- display timing signals (measurement condition : cl=20pf) no. item symbol min typ max unit note gck1in, gck2in : frequency f gcki 5 40 mhz 1 1 gck1in, gck2in : cycle time t cgcki 25 200 ns 2 2 gck1in, gck2in : clock high level width t whgcki 8 ns 3 gck1in, gck2in : clock low level width t wlgcki 8 ns 4 hsin_n, vsin_n, dri5-0, dgi5-0, dbi5-0: input data setup time t sdi 3 ns 5 hsin_n,vsin_n,dri5-0, dgi5-0, dbi5-0: input data hold time t hdi 1 ns gck1out: delay time t dgck1o 0 20 ns 6 gck2out: delay time t dgck2o 0 20 ns gck1out : frequency f gck1o 5 40 mhz gck1out : cycle time t cgck1o 25 200 ns gck2out : frequency f gck2o 5 40 mhz 7 gck2out : cycle time t cgck2o 25 200 ns 8 gck1out, gck2out : clock duty t dugcko 45 55 % 3 9 ys_n, csync_n, vsync_n, blank_n, dro5-0, dgo5-0, dbo5-0: output delay time t ddisp1 9 ns 10 ys_n, csync_n, vsync_n, blank_n, dro5-0, dgo5-0,dbo5-0: output hold time t hdisp1 0 ns note 1) fulfill a condition ? f sdck ? f gck1o 2 note 2) fulfill a condition ? t csdck 2 ? t cgck1o note 3) in the cases of other than analog synchronization gck1in or gck2in inputs gck1out or gck2out outputs 6 9 10 6 6 88 7 4 5 23 1 inputs hsin_n, vsin_n, dri5-0, dgi5-0, dbi5-0 outputs ys_n, csync_n, vsync_n, blank_ n, dro5-0, dgo5-0, dbo5-0
ygv628b -23- analog characteristics in avdp7, r, g, and b pin is an output pin for an analog signal. rgb pin output characteristics item condition min type max unit resolution 8 bit settling time 20 ns output propagation delay time -5 3 ns output voltage amplitude (vp-p) 0.7 v max output voltage (v white ) 0.7 v min output voltage (v black ) 0 v vp-p deviation of r, g, b r l = 37.5 ? c l = 30 pf i ref = -9.38ma additional capacity of gck1out = 20pf 3 % settling time is defined as the interval between the point at which dac output level comes up to 50% and the point at which the output level reaches and stays within 1 lsb centered on the resulting output level. output propagation delay time is defined as the interval between the rising edge of gck1out and the point at which dac output level comes up to 50%. gck1out r g b settling time output propagation delay time ? 1 lsb ? 1 lsb 50 % measurement circuit r,g,b rl cl
ygv628b -24- p p a a c c k k a a g g e e o o u u t t l l i i n n e e d d r r a a w w i i n n g g
ygv628b -25-
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